Semiconductor memory devices used for storing different types of data are generally classified a volatile and nonvolatile. Volatile memory devices lose data stored therein when the power thereto is interrupted. In contrast, nonvolatile memory devices retain their data even when power thereto is interrupted. Thus, nonvolatile memory devices may be useful for applications, such as mobile phones, that have intermittent access to power supplies, i.e., where the battery may run out before the device can be charged or plugged in.
Types of nonvolatile memory devices may include flash memory devices, ferroelectric memory devices, phase-changeable memory devices, magnetic memory devices, and the like. Flash memory devices may be used to enhance integration because they use unit cells similar to metal oxide semiconductor (MOS) transistors without additional elements for storing information. Flash memory devices may be classified into floating-gate and floating-trap types in accordance with structural features of the memory cell. Floating-gate flash memory devices have a floating gate isolated by an insulation film between a semiconductor substrate and a control gate, into which data is stored by implanting charges. Floating-trap flash memory devices store data by implanting charges into a trap that is formed in a non-conductive charge storage film between a semiconductor substrate and a gate electrode.
Referring to FIG. 1, a cross section illustrating a conventional cell transistor of a floating-trap memory device will be discussed. Referring to FIG. 1, N-type impurities are implanted into regions of a P-type semiconductor substrate 1, forming source and drain regions S and D, respectively. A cell gate-insulation film 3 and a cell gate-conductive film 4 are formed between the source and drain regions S and D, respectively. The cell gate-insulation film 3 includes a tunneling insulation film 3a, a charge storage film 3b, and a blocking insulation film 3c. 
There are potential barriers at the interfaces among the semiconductor substrate 1, the tunneling insulation film 3a, the charge storage film 3b, the blocking insulation film 3c, and the cell gate-conductive film 4. In storing data, electrons are accelerated toward the drain region D from the source region S. The accelerated electrons are captured by the charge storage film 3b, after passing through the potential barrier of the tunneling insulation film 3a. In contrast, in erasing data, the electrons captured by the charge storage film 3b are forced to penetrate the tunneling insulation film 3a. In reading data, a threshold voltage of a selected cell transistor is measured. The threshold voltage is variable in accordance with whether the electrons are being captured or not.
Such a flash memory device has a peripheral circuit for driving memory cells. The peripheral circuit may include low-voltage transistors operable in a read mode and high-voltage transistors operable in program/erase modes. FIG. 2 is a cross section illustrating a structure of the conventional floating-trap memory device including a peripheral circuit.
Referring to FIG. 2, a cell field region Cell, a high-voltage field region Hv, and a low-voltage field region Lv represent regions where cell transistors, high-voltage transistors, and low-voltage transistors are formed, respectively. As illustrated in FIG. 2, device isolation films 2 are formed in the semiconductor substrate 1 to define active regions therein. The cell gate-insulation film 3 and the cell gate-conductive film 4 are formed in the cell field region Cell; a high-voltage gate-insulation film 5 and a high-voltage gate-conductive film 6 are formed in the high-voltage field region Hv; and a low-voltage gate-insulation film 7 and a low-voltage gate-conductive film 8 are formed in the low-voltage field region Lv. The cell gate-insulation film 3 includes a tunneling insulation film 3a, a charge storage film 3b, and a blocking insulation film 3c. The high-voltage gate-insulation film 5 and the low-voltage gate-insulation film 7 include a single layer. The high-voltage gate-insulation film 5 is thicker than the low-voltage gate-insulation film 7 in order to enhance a characteristic of voltage endurance because the high-voltage transistors operate with a voltage boosted up from an external source voltage. Channel-stopping regions 9, into which impurities have been implanted, are formed under the device isolation films 2 of the high-voltage field region Hv. The channel-stopping regions 9 are provided for the purpose of maintaining isolation conditions between transistors, considering the fact that high-voltage differences are generated between adjacent transistors of the high-voltage field region Hv.
Conventional flash memory devices may have problems in conjunction with manufacturing processes. For example, processing steps in the fabrication of the flash memory device illustrated in FIG. 2 may be complicated due to the fact that the gate-insulation films 3, 5, and 7 have different thicknesses and the structures are used in the cell field region Cell, the low-voltage field region Lv, and the high-voltage field region Hv. For example, the high-voltage gate-insulation film 5 is formed on the semiconductor substrate 1; the high-voltage gate-insulation film 5 is removed from the cell and low-voltage field regions while blocking the high-voltage field region; the low-voltage gate-insulation film 7 is formed in the cell and low-voltage field regions; the low-voltage gate-insulation film 7 is removed from the cell field region while blocking the low and high-voltage field regions; and the cell gate-insulation film 3 is removed from the high and low-voltage field regions after depositing the cell gate-insulation film 3 on the semiconductor substrate 1. Furthermore, impurities are implanted for the channel-stopping regions 9 or for the threshold voltage control. The impurities for the channel-stopping regions 9 are implanted through the device isolation films 2 in the high-voltage field region Hv, causing the fabrication process to be complicated.
Furthermore, conventional flash memory devices like the device of FIG. 2 fabricated using conventional methods, may be regarded as being insufficient or having deficient operational characteristics. For example, in highly integrated devices a distance between the device isolation films 2, which corresponds to a channel width of a transistor in FIG. 2, may become narrower. The reduction of channel width may cause the amount of current to decrease during an operation of the transistor. Moreover, as a size of the device is decreased, a channel length between the source and drain regions S and D is also gradually decreased, which may cause a short channel effect therein.